1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device, particularly, to a method of manufacturing a semiconductor device having a resistor element.
2. Description of the Related Art
An element having a relatively high resistance value made of a polysilicon layer (hereafter, referred to as a polysilicon resistor layer) has been known as a resistor element for forming an LSI circuit mounted with an analog circuit. This polysilicon resistor layer is broadly used since forming this polysilicon resistor layer in an element separation region reduces the area of an element formation region and realizes large scale integration and reduced parasitic capacitance.
In the general LSI circuit, not only the polysilicon resistor layer but also active elements, such as a MOS transistor or a bipolar transistor, are formed on the same semiconductor substrate. Hereafter, descriptions will be given on an example of a conventional process of manufacturing a semiconductor device having a polysilicon resistor layer and a MOS transistor formed on the same semiconductor substrate, referring to FIGS. 6 to 8.
As shown in FIG. 6, field insulation films 101 for separating elements are formed on a semiconductor substrate 100 by a LOCOS method or the like. A gate insulation film 102 for the MOS transistor is formed on a surface of the semiconductor substrate 100 in a region surrounded by the field insulation films 101 by a thermal oxidation method or the like. Then, a polysilicon layer is formed on the whole surface of the semiconductor substrate 100, and ion implantation is performed thereto so as to provide resistor elements with desired resistance values. Then, the polysilicon layer is patterned by dry-etching or the like to form a polysilicon resistor layer 103 on the field insulation film 101 and form a gate electrode 104 on the gate insulation film 102.
Then, as shown in FIG. 7, for enhancing electric connection in contact formation regions of the polysilicon resistor layer 103, ion implantation is performed to the polysilicon resistor layer 103 using a resist film 105 as a mask to form low resistance regions 106a to 106c (regions where high concentration of impurities are implanted) on the polysilicon resistor layer 103.
Ion implantation is also performed to a MOS transistor formation region at the same time as when the low resistance regions 106a to 106c are formed, to form a source region 107 and a drain region 108. Then, heat treatment (annealing) is performed for about an hour at high temperature (e.g. 950° C.) to activate the implanted impurities.
Then, as shown in FIG. 8, an interlayer insulation film 109 is formed on the whole surface of the semiconductor substrate 100, and then contact holes 110 are formed therein in desired positions above the polysilicon resistor layer 103, the source region 107 and the drain region 108. Then, a metal wiring 116 is formed in each of the contact holes 110, and thus the polysilicon resistor layer 103 and the MOS transistor are electrically connected to the other elements. FIG. 9 is a schematic top plan view of the semiconductor device formed by this process. The relevant technology is disclosed in the Japanese Patent Application Publication No. H5-129294.
A resistance value R of a resistor element is obtained by R=Rs×L/W. The Rs is a sheet resistance (Ω/sp), the L is the length of the resistor element and the W is the width thereof. The patterning size (the sheet resistance Rs, the length L and the width W) of the above described polysilicon resistor layer 103 is designed in advance so as to provide the resistor element with a desired resistance value R, and not changed in the manufacturing process.
Conventionally, as shown in FIG. 7, the resistor elements are designed by defining lengths X and Y between the regions that are ion-implanted using the resist film 105 as the lengths L of the resistor elements. The X is the length between the adjacent low resistance regions 106a and 106b and the Y is the length between the low resistance regions 106b and 106c, and X=1200 μm and Y=70 μm, for example.
In the above described conventional manufacturing process, however, high temperature heat treatment (annealing) is necessarily performed after the low resistance regions are formed in order to activate the impurity regions of the other active elements. Therefore, in the high temperature heat treatment, the impurities in each of the low resistance regions 106a to 106c are diffused in a lateral direction by a certain distance Z to form low resistance regions 115a to 115c as shown in FIGS. 8 and 9. Therefore, the previously designed lengths X and Y of the resistor elements are shortened to X′ and Y′, thereby causing a difference between a theoretical resistance value and a measured resistance value. This difference occurs more prominently in the finer resistor elements, causing a serious problem especially for obtaining a bit of voltage by resistor-division.
Although it is possible to prevent this difference by designing the longer lengths X and Y of the low resistance regions in advance, this case causes a problem that the polysilicon resistor layer 103 occupies a large area to increase a die area.
The invention is directed to reduction of the difference between the theoretical resistance value and the measured resistance value of the resistor element and size reduction of the resistor element.